For Shrikanth Ganapathy, research gives him a feeling of great freedom. This feeling has only grown stronger since he embarked on his experience in the city of Barcelona.
Holder of a degree in electronics and communications from Anna University (India), he is a researcher with the Architectures and Compilers (ARCO) Group and is writing his PhD within the framework of the Terascale Reliable Adaptive Memory Systems (TRAMS) research project, which aims to ensure that the memories of the teraflop-capable nanometric processors of the future are robust, reliable, energy efficient, fault tolerant and equipped with a variety of advanced features.
As a result of the constant shrinking of transistors and ensuing improvements in their performance, in accordance with Moore’s Law (named after Gordon Moore, founder of Intel Corporation), within the next decade a single chip should be able to perform trillions of operations per second, thereby enabling data flows of several trillion bytes per second. Such impressive computing capacities will not only transform the processing flows at major data and computer-service centres, but also the power consumption and functional capacity of personal computers, communication devices and all other electronic devices with entertainment and home applications.